Process variation is a problem for high-speed digital logic implemented in a semiconductor integrated circuit. The high-speed digital logic should be designed so that it operates correctly in all regions of an integrated circuit wafer, in particular in the worst corners of the wafer where process parameters can cause transistors to be slowest and temperature can be highest. However, this can result in a design in which a high current is used in other areas of the wafer where transistors can be faster and temperature can be lower. Moreover, the need for an integrated circuit to operate over a range of temperatures and frequencies can result in a design in which a high current is used during operation at normal temperature and frequencies. This problem can be particularly severe for an integrated circuit that is required to operate at a high frequency, such as several gigahertz, where low power operation is more difficult to achieve. There is, therefore, a requirement to reduce power consumption of integrated circuits subject to process, temperature and frequency variations.